1. Technical Field
An internal voltage supply circuit is disclosed for controlling an internal voltage supplied to an input/output sense amplifier in accordance with a current drive capability of a semiconductor device.
2. Description of the Related Art
Generally, manufacturing conditions or environments during the semiconductor chip manufacturing processes may lead to differences in performance among the semiconductor devices. Furthermore, as a semiconductor device operates at a high speed, such a different quality in manufacturing may degrade performance of the semiconductor device, such as current drive capability. In particular, this problem may occur in the core circuit of a semiconductor device in an active operation, which will hereinafter be described with reference to FIGS. 1 and 2.
FIG. 1 shows a core circuit of a conventional semiconductor device, more particularly a circuit that includes an input/output sense amplifier and a circuit for supplying a voltage to the input/output sense amplifier. As shown in FIG. 1, the input/output sense amplifier 120 is operated by receiving, as a source voltage, a high voltage Vpp or core voltage Vcore applied from the sense amplifier voltage supply circuit, denoted by reference numeral 110. This configuration is adopted and used currently in dynamic random access memory (DRAM) products of 533 MHz or more, beginning with products prior to synchronous DRAMs (SDRAMs).
The circuit of FIG. 1 is operated in the following manner. First, if a word line is turned on, then the sense amplifier 120 senses a potential difference between a bit line BIT and a complementary bit line/BIT. At this time, an N-channel Metal-Oxide Semiconductor (NMOS) transistor N11 is first turned on in response to a high voltage enable signal SAP1 to apply the high voltage Vpp as the source voltage to the sense amplifier 120, thereby causing the level of a node A to become the level of the high voltage Vpp. Thereafter, when a certain period of time has elapsed, a core voltage enable signal SAP2 is enabled to turn on an NMOS transistor N12, whereas the high voltage enable signal SAP1 is disabled to turn off the NMOS transistor N11. As a result, the core voltage Vcore is applied as the source voltage to the sense amplifier 120, so the level of the node A is maintained at the level of the core voltage Vcore.
FIG. 2 shows signal waveforms at respective parts of the circuit of FIG. 1, based on the high voltage enable signal SAP1 and core voltage enable signal SAP2. As can be seen from this drawing, a voltage at the node A, which is the source voltage of the sense amplifier 120, rises to the high voltage Vpp level in an enable period of the high voltage enable signal SAP1 and then falls to and is maintained at the core voltage Vcore level in a disable period of the high voltage enable signal SAP1.
However, the above-mentioned conventional semiconductor device has a disadvantage in that it may be degraded in its electrical characteristics, such as alternating current (AC) characteristics, or increased in current consumption, because a high voltage Vpp application period is constant irrespective of differences in performance, such as a current drive capability, among semiconductor devices resulting from different environments or conditions about a semiconductor chip manufacturing processes. That is, in the case where the conventional semiconductor device is poor in its overall performance including current drive capability due to conditions of the manufacturing process, the high voltage Vpp is so insufficiently supplied as to cause a shortage in the current drive capability. On the contrary, in the case where the conventional semiconductor device has good overall performance, the high voltage Vpp is so excessively supplied as to increase unnecessary current consumption.